Low Power BIST based Pattern Generation for Low Power VLSI Architecture
نویسنده
چکیده
In the semiconductor manufacturing industry recently remarkable technological developments like, feasibility of millions of transistors and various other components to be integrated on a Chip with enormous packaging options than it is tested by BIST. The role of the BIST circuit is to reduce the cost by reducing the testing interval and the complexity of testing. The power dissipated in a circuit during testing mode is considerably larger than that dissipated in the operational mode. This increase in power dissipated can be recognized to the decreased correlation between the random patterns generated in the test mode. Hence, the idea behind this paper is to design a DFT circuit that will help in decreasing the switching activities in the test mode in order to limit the power dissipation.
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